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55 KiB
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55 KiB
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{{
Modified Tiny Basic for use with Propeller Demo Board and Hydra.
I2C and SPI driver initialization & interface object derived from Propeller OS.
Copyright (c) 2009 Michael Green. See end of file for terms of use.
}}
'' 2006/09/24 - Corrected action table for i2cRead0Cmd
'' 2006/10/02 - Improved assembly comments. Changed i2cReset, i2cStop
'' 2006/11/02 - Changed data setup time. Changed i2cReset timing
'' 2006/11/03 - Changed read/write method speed to 100KHz
'' 2006/11/04 - Added checkPresence, writeWait, and computeTimes methods
'' 2006/11/06 - Limited boot loading to 32K - 16 (OS uses last 16 bytes)
'' Added ioVerifyCmd and verifyEEPROM method
'' 2006/11/09 - Modified boot and verify to use the minimum of the actual
'' length of the program stored in vbase ($0008) or the
'' specified byte count.
'' Note also that these routines don't know about option bits.
'' 2006/11/10 - Now control block address is passed to start routine
'' 2007/01/09 - Added SPI routines for SD card FAT access
'' 2007/01/13 - Corrected checksum when ioBoot or ioVerify
'' 2007/01/13 - Stores stack marker & clears VAR area on ioBootCmd
'' 2007/02/06 - Stores stack marker & clears VAR area on ioSpiBoot
'' 2007/02/13 - Changed the way verify mode was done, combined code
'' 2007/02/20 - Added ioStopLdr option to stop the loader's cog
'' 2007/02/22 - Corrected bootSDCard. Needs start and initSDCard calls first.
'' 2009/04/04 - spiDoStop modified per Cluso99 to turn off card
'' 2009/07/21 - I2C setup times modified per Nick Mueller's timing tests
'' Default I2C bus timing changed to 400KHz. Thanks Nick.
'' This portion is normally run only once during initialization and the driver remains
'' resident in a cog. These routines can be used completely independently of the rest
'' of the Propeller OS. The start routine here expects the address of a 2 long area
'' to be used for passing information to the I/O routines in the COG. This area should
'' be located in an area of memory not expected to be overlaid by data or a program that
'' might be loaded since the COG routines will be accessing this information after an
'' operation has completed.
'' This object provides an I2C EEPROM read/write routine that can handle both 100KHz and
'' 400KHz bus speeds and EEPROM page sizes of 64, 128, or 256 bytes (or no paging/no delay
'' as with Ramtron serial RAM). The SPIN interpreter can be started after reading, either
'' in the same COG used by these routines or in a free COG. The control information is
'' passed in a 2 long parameter block whose address is passed to the COG when it is started.
'' The parameter block is updated when the operation is completed. Note that these are shown
'' here as they appear in a long value rather than the order of the bytes in memory.
'' -------------------------------------------------------------------
'' | cmd/status | I/O pin / device / address |
'' -------------------------------------------------------------------
'' | byte count | HUB address |
'' -------------------------------------------------------------------
'' The EEPROM address is in the same format used by other routines with the I/O pin pair
'' in bits 21..19, the device address in bits 18..16, and the 64K address in bits 15..0.
'' Note that the I/O pin pair is the number of the SCL pin divided by 2. The SDA pin is
'' always the next higher numbered pin. The command code is in the low order bits of the
'' high order byte of the first long (see ioCmdMask). This is always non-zero to indicate
'' that a command is to be performed by the COG routines. When the command is finished,
'' this is set to zero. The errorFlag bit is set to one if a NAK was read after a write
'' transfer. This is the only error reported by these routines. A read operation and
'' zero-length writes do involve several write transfers for addressing, but the data
'' read transfer has no error checking.
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